The present invention relates to an improved structure of power supply wirings in a semiconductor integrated circuit device.
A semiconductor integrated circuit device is usually supplied with at least two D.C. power supply voltages of, e.g., Vcc and ground potential. These voltages are applied to electrode pads provided on a semiconductor chip, or substrate, of the integrated circuit device and transmitted to respective circuits within the chip through respective power supply wiring layers formed on the chip. A power supply wiring is composed of two or more main wiring layers having a broader width, one of which runs along the edge or edges of the chip for the circuits (e.g. clock generator circuits and input and output circuits in case of a memory device) provided at the peripheral portions of the chip, the other running in the center portion of the chip for the circuits (e.g. a plurality of memory cells arranged in a matrix shape and decoder circuits in case of the memory device) provided at the center portion, and branch wiring layers having a narrower width and connected between the main wiring layers and circuit element in the respective circuits. The electrode pad, or the bonding pad, is connected to a predetermined portion of the main wiring layer, and a bonding wire is bonded to the bonding pad. Since the respective circuits require both of the two D.C. power supply voltages, four main wiring layers often run in parallel. The first main wiring layer is positioned in the most outer peripheral area, or nearest the edge of the chip, to supply the ground potential to the circuits at the peripheral portions. The second main wiring layer is positioned inner the first layer to supply the Vcc potential to the circuits at the peripheral portions. The third and fourth main layer are positioned inner the second layer to supply the ground potential and Vcc potential to the circuits at the central portions, respectively. Further a plurality of signal wiring layers such as clock signal lines, data signal lines, and address signal lines extend in the gap space of the main wiring layers. The main wiring layers and the signal wiring layers are at the same level and made of a metallic film such as an aluminum film to reduce the electrical resistance. Namely, these wiring layers are simultaneously formed by patterning an aluminum film of 1.2 .mu.m thickness, for example, at the same process step.
In the conventional semiconductor device, the first and third main wiring layers for supplying the ground potential are electrically connected with a bridging wiring layer which is made of aluminum at the same level as the main wiring layer and has a broader width as that of the main wiring layer. Therefore, the second main wiring layer and signal wiring layers must be cut away at the bridging wiring layer and must be connected to each other with a polycrystalline wiring layer at a different level or with a diffusion layer in the chip underneath the bridging wiring layer. Namely, the so-called "tunnel wiring structure" must be provided for the signal line, and therefore, the resistance of the signal line becomes large. In practice, the bridging wiring layer has about 30 .mu.m width, and accordingly, the length of the polycrystalline or diffusion wiring layer is more than 30 .mu.m. Therefore, the resistance of the signal line becomes several hundreds ohms at this portion. In the recent very large scale integrated circuit device, the load capacitance of the signal line has been enhanced to about several ten picofarads (pF), for example. In this case, if the resistance of the signal line is one kilo-ohms (K.OMEGA.), the time constant becomes a large value such as several ten nano seconds (n sec), and also the value of the access time become long. The value must be decreased by reducing the resistance of the signal line. Therefore, it is necessary to eliminate the above mentioned tunnel wiring structure from the signal line.
On the other hand, in the recent VLSI device, a large surge current such as several hundreds milliamperes (mA) in peak value at ten nano-seconds (n sec) is apt to flow and induces an inverse voltage in the ground line by inductances of bonding wires and leads of the package. Therefore, the ground potential line would be elevated, in the extreme case, by 0.6 to 1.0 volt (V). This phenomenon causes error operation such as multi select phenomenon in the decoder circuit and restricts a high speed operation.